Integrated Memory Comprising Gated Regions Between Charge-Storage Devices and Access Devices

ABSTRACT

Some embodiments include an integrated assembly having an access transistor. The access transistor has a first source/drain region gatedly coupled with a second source/drain region. A digit line is coupled with the first source/drain region. A charge-storage device is coupled with the second source/drain region through an interconnect. The interconnect includes a length of a semiconductor material. A protective transistor gates a portion of the length of the semiconductor material.

RELATED PATENT DATE

This patent is related to U.S. provisional application Ser. No.62/717,629 which was filed Aug. 10, 2018.

TECHNICAL FIELD

Integrated memory comprising gated regions between charge-storagedevices and access devices.

BACKGROUND

Memory is utilized in modern computing architectures for storing data.One type of memory is Dynamic Random-Access Memory (DRAM). DRAM mayprovide advantages of structural simplicity, low cost and high speed incomparison to alternative types of memory.

DRAM may utilize memory cells which each have one capacitor incombination with one transistor (so-called 1T-1C memory cells), with thecapacitor being coupled with a source/drain region of the transistor. Anexample 1T-1C memory cell 2 is shown in FIG. 1 , with the transistorlabeled T and the capacitor labeled C. The capacitor has one nodecoupled with a source/drain region of the transistor, and has anothernode coupled with a common plate, CP. The common plate may be coupledwith any suitable voltage, such as a voltage within a range of fromgreater than or equal to ground to less than or equal to VCC (i.e.,ground≤CP≤VCC). In some applications, the common plate is at a voltageof about one-half VCC (i.e., about VCC/2). The transistor has a gatecoupled to a wordline WL (i.e., access line), and has a source/drainregion coupled to a bitline BL (i.e., digit line or sense line). Inoperation, an electrical field generated by voltage along the wordlinemay gatedly couple the bitline to the capacitor during read/writeoperations.

Another prior art 1T-1C memory cell configuration is shown in FIG. 2 .The configuration of FIG. 2 shows two memory cells 2 a and 2 b; with thememory cell 2 a comprising a transistor T1 and a capacitor C1, and withmemory cell 2 b comprising a transistor T2 and a capacitor C2. WordlinesWL0 and WL1 are electrically coupled with the gates of transistors T1and T2, respectively. A connection to a bitline BL is shared by thememory cells 2 a and 2 b.

The memory cells described above may be incorporated into memory arrays,and in some applications the memory arrays may have open bitlinearrangements. An example integrated assembly 9 having open bitlinearchitecture is shown in FIG. 3 . The assembly 9 includes two laterallyadjacent memory arrays (“Array 1” and “Array 2”), with each of arraysincluding memory cells of the type described in FIG. 2 (not labeled inFIG. 3 in order to simplify the drawing). Wordlines WL0-WL7 extendacross the arrays, and are coupled with wordline drivers. Digit linesD0-D8 are associated with the first array (Array 1), and digit linesD0*-D8* are associated with the second array (Array 2), Sense amplifiersSA0-SA8 are provided between the first and second arrays. Digit lines atthe same height are paired within one another and compared through asense amplifier (e.g., digit lines D0 and D0* are paired with oneanother and compared with the sense amplifier SA0). In a read operation,one of the paired digit lines may serve as a reference in determiningelectrical properties (e.g., voltage) of the other of the paired digitlines.

A problem which may be encountered with conventional DRAM is thatoperation along a row of memory cells may problematically disturb anadjacent row of memory cells, and may eventually result in data lossfrom one or of the memory cells along the adjacent row. It would bedesirable to develop arrangements which avoid such data loss.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic diagram of a prior art memory cell having 1transistor and 1 capacitor.

FIG. 2 is a schematic diagram of a pair of prior art memory cells whicheach have 1 transistor and 1 capacitor, and which share a bitlineconnection.

FIG. 3 is a schematic diagram of a prior art integrated assembly havingopen bitline architecture.

FIG. 4 is a schematic diagram of an example memory array illustrating anexample inter-cell disturb problem.

FIG. 5 is a diagrammatic cross-sectional side view showing a region ofan example integrated assembly which may be within the memory array ofFIG. 4 .

FIG. 6 is a diagrammatic cross-sectional side view showing a region ofan example integrated assembly.

FIG. 7 is a schematic diagram illustrating a region of an example memoryarray which may comprise the assembly of FIG. 6 .

FIG. 8 is a diagrammatic cross-sectional side view showing a region ofan example integrated assembly which may be within the memory array ofFIG. 7 , and which may be a specific example of the more genericassembly of FIG. 6 .

FIG. 9 is a diagrammatic cross-sectional side view showing a region ofan example integrated assembly.

FIG. 10 is a schematic diagram illustrating a region of an examplememory array which may comprise the assembly of FIG. 9 .

FIG. 11 is a diagrammatic cross-sectional side view showing a region ofan example integrated assembly which may be within the memory array ofFIG. 10 , and which may be a specific example of the more genericassembly of FIG. 9 .

DETAILED DESCRIPTION OF THE ILLUSTRATED EMBODIMENTS

Some embodiments include integrated assemblies having memory cells whicheach include an access transistor associated with a charge-storagedevice (e.g., a capacitor). Each memory cell also includes a protectivetransistor (or other suitable switch) to control current flow betweenthe charge-storage device and a source/drain region of the associatedtransistor, which may alleviate or prevent the problematic data lossdiscussed above in the Background section. Example embodiments aredescribed with reference to FIGS. 4-11 .

Referring to FIG. 4 , a region of a memory array 10 is shown to comprisea plurality of digit lines (DL0, DL1, DL1 and DL3), a plurality ofwordlines (WL0, WL2 and WL3). Memory cells 12 are addressed by thewordlines and digit lines. Each of the memory cells comprises atransistor and a capacitor, and is analogous to the memory cells 2 a and2 b described above with reference to FIG. 2 . The digit lines extend tosense amplifiers (SA0, SA1, SA2 and SA3), and the wordlines extend to aRow Driver. In some embodiments, the memory array 10 be considered tocorrespond to one of the arrays described above with reference to FIG. 3(i.e., Array-1 or Array-2).

The capacitors have nodes connected to reference structures 19. Thereference structures may comprise any suitable voltage; and in someembodiments may correspond to common plates of the type described abovewith reference to FIGS. 1 and 2 .

A box 14 is provided around the row addressed by the wordline WL0 toindicate that such wordline is activated. The activation of the wordlineWL0 accesses the memory cells 12 along such wordline for variousoperations (e.g., read/write operations, refresh operations, etc.).Often, some rows of a memory array will be activated much morefrequently than others. The rows which are frequently activated may bereferred to as being “hammered” in that they experience an exceptionalamount of usage. As discussed above in the Background section, a problemwhich may occur is that operation (i.e., activation) of one row ofmemory cells may problematically disturb an adjacent row of memorycells. Such problem may be particularly likely to manifest adjacent rowswhich are “hammered”.

FIG. 5 shows a cross-section along a region of the memory array 10 ofFIG, 4, and shows each of the memory cells 12 comprising a capacitor 16and a transistor 18. The capacitors 16 may be considered to be examplesof charge-storage devices which may be utilized in the memory cells 12.In other embodiments, other suitable charge-storage devices may beutilized; with examples of other suitable charge-storage devicesincluding phase change materials, conductive-bridging materials, etc.

The transistors and capacitors are supported by a base 30 comprisingsemiconductor material 32. The semiconductor material 32 may compriseany suitable composition(s); and in some embodiments may comprise,consist essentially of, or consist of one or more of silicon, germanium,III/V semiconductor material (e.g., gallium phosphide), semiconductoroxide, etc.; with the term III/V semiconductor material referring tosemiconductor materials comprising elements selected from groups III andV of the periodic table (with groups III and V being old nomenclature,and now being referred to as groups 13 and 15). For instance, thesemiconductor material 32 may comprise, consist essentially of, orconsist of monocrystalline silicon.

The base 30 may be referred to as a semiconductor substrate. The term“semiconductor substrate” means any construction comprisingsemiconductive material, including, but not limited to, bulksemiconductive materials such as a semiconductive wafer (either alone orin assemblies comprising other materials), and semiconductive materiallayers (either alone or in assemblies comprising other materials). Theterm “substrate” refers to any supporting structure, including, but notlimited to, the semiconductor substrates described above. In someapplications, the base 30 may correspond to a semiconductor substratecontaining one or more materials associated with integrated circuitfabrication. Such materials may include, for example, one or more ofrefractory metal materials, barrier materials, diffusion materials,insulator materials, etc.

The illustrated transistors have gates 20 along the wordlines WL0-WL3,and have source/drain regions 22 extending into the semiconductormaterial 32 of the base 30. The source/drain regions may compriseconductively-doped regions within the semiconductor material 32.

The gates 20 are spaced from the semiconductor material 32 by dielectricmaterial (i.e., insulative material) 24. The dielectric material 24 maycomprise any suitable composition(s); and in some embodiments maycomprise, consist essentially of, or consist of silicon dioxide, Thedielectric material 24 may be referred to as gate dielectric material.

The transistors 18 have channel regions 26 beneath the gates 20; and thesource/drain regions of each of the transistors are gatedly coupled toone another through the channel region between them. In the illustratedembodiment, the channel regions 26 extend horizontally between thesource/drain regions 22.

The capacitors 16 are coupled with vertically-extending interconnects28, which in turn are coupled with some of the source/drain regions 22.Others of the source/drain regions 22 are coupled with the digit lineDL0 through vertically-extending interconnects 34. The interconnects 28and 34 may comprise any suitable electrically conductive composition(s).

The transistors 18 are in paired relationships such that two adjacenttransistors share a common connection to the digit line. For instance,two of the transistors are labeled as 18 a and 18 b, and suchtransistors are paired with one another. The transistors 18 a and 18 bmay be referred to as first and second transistors, respectively. Thetransistors 18 a and 18 b together comprise three source/drain regions(labeled 22 a, 22 b and 22 c). The source/drain regions 22 a, 22 b and22 c may be referred to as first, second and third source/drain regionsrespectively. The second source/drain region 22 b is shared between thefirst and second transistors 18 a and 18 b, and is coupled with thedigit line DL0. The first source/drain region is coupled with a firstcapacitor (labeled 16 a), and the third source/drain region is coupledwith a second capacitor (labeled 16 b).

The channel regions of the first and second transistors 18 a and 18 bare labeled 26 a and 26 b, and may be referred to as first and secondchannel regions, respectively.

The memory cells comprising the first and second transistors 18 a and 18b are labeled as memory cells 12 a and 12 b, and may be referred to asfirst and second memory cells, respectively.

Isolation material 36 extends into the base 30 and separatespaired-transistor-arrangements from one another. The isolation material36 may comprise any suitable composition(s); and in some embodiments maycomprise, consist essentially of, or consist of silicon oxide.

The wordline WL0 is surrounded by the box 14 to indicate that suchwordline is activated. Another box 15 is provided within the base 30proximate the wordline WL1 to indicate that such region may be disruptedduring the activation of the wordline WL0. The disruption within theregion of box 15 may lead to junction leakage and/or to other mechanismswhich enable discharge of current from the capacitor 16 b into the base30 (as is diagrammatically illustrated utilizing arrows 37), and thusmay problematically lead to loss of data from the memory cell 12 b.

Some embodiments include provision of protective transistors between thecapacitors 16 and the associated source/drain regions (e.g., along theinterconnects 28) to alleviate the problematic discharge of current fromthe capacitors into the base while adjacent rows are “hammered”. Forinstance, FIG. 6 shows a region of the memory array 10 modified toinclude protective transistors 40 between the capacitors 16 and thesource/drain regions 22; and specifically along the interconnects 28.The protective transistors coupled with the source/drain regions 22 aand 22 c are labeled as transistors 40 a and 40 b, and may be referredto as first and second protective transistors, respectively.

In some embodiments, the transistors 18 may be referred to as accesstransistors in order to distinguish them from the protective transistors40.

The interconnects 28 are shown to be extended to include pillars 42 ofsemiconductor material 44. The pillars 42 extend vertically, and may bereferred to as vertically-extending lengths of the semiconductormaterial 44. In other embodiments, the lengths of semiconductor material44 may extend in directions other than vertically.

In the shown embodiment, each of the interconnects 28 includes a firstconductive material 46 under the semiconductor material 44. The firstconductive material 46 may comprise any suitable electrically conductivecomposition(s); such as, for example, one or more of various metals(e.g., titanium, tungsten, cobalt, nickel, platinum, ruthenium, etc.),metal-containing compositions (e.g., metal silicide, metal nitride,metal carbide, etc.), and/or conductively-doped semiconductor materials(e.g., conductively-doped silicon, conductively-doped germanium, etc.).In some embodiments, the first material 46 may comprise a samecomposition as the semiconductor material 44, and may be aconductively-doped extension of the semiconductor material 44.

The semiconductor material 44 may comprise any suitable composition(s);and in some embodiments may comprise, consist essentially of, or consistof one or more of silicon, germanium, III/V semiconductor material(e.g., gallium phosphide), semiconductor oxide, etc.; with the termsemiconductor material referring to semiconductor materials comprisingelements selected from groups and V of the periodic table (with groupsIII and V being old nomenclature, and now being referred to as groups 13and 15). In some example embodiments, the semiconductor material 44 maycomprise polycrystalline silicon.

In some embodiments, the materials 44 and 46 may be considered togetherto form the interconnects 28 which extend between the source/drainregions 22 and the capacitors 16. In the shown embodiment, theinterconnect associated with the capacitor 16 a is labeled as aninterconnect 28 a, and the interconnect associate with the capacitor 16b is labeled as an interconnect 28 b. The interconnects 28 a and 28 bmay be referred to as first and second interconnects, respectively; andare coupled with the first and third source/drain regions 22 a and 22 c.The pillars (i.e., semiconductor-material lengths) 42 a and 42 b withinthe interconnects 28 a and 28 b may be referred to as first and secondpillars (or as first and second semiconductor-material lengths),respectively; and the semiconductor materials 44 a and 44 b within suchpillars may be referred to as first and second semiconductor materials,respectively.

The protective transistors 40 include conductive gating material 48, andinclude insulative material 50 between the gating material 48 and thesemiconductor material 44 of the pillars 42.

The gating material 48 may comprise any suitable electrically conductivecomposition(s); such as, for example, one or more of various metals(e.g., titanium, tungsten, cobalt, nickel, platinum, ruthenium, etc.),metal-containing compositions (e.g., metal silicide, metal nitride,metal carbide, etc.), and/or conductively-doped semiconductor materials(e.g., conductively-doped silicon, conductively-doped germanium, etc.).The gating material 48 is configured as transistor gates 49.

The insulative material 50 may comprise any suitable composition(s); andin some embodiments may comprise, consist essentially of, or consist ofsilicon dioxide. The insulative material 50 may be referred to as gatedielectric material in some embodiments.

The protective transistors 40 comprise source/drain regions 52 and 54,and channel regions 56 between the source/drain regions. Thesource/drain regions 54 may be referred to as upper source/drainregions, and the source/drain regions 52 may be referred to as lowersource/drain regions. The channel regions 56 extend vertically betweenthe upper and lower source/drain regions. In some embodiments, theprotective transistors 40 may be referred to as vertical transistors dueto the vertically-extending channel regions 56; and the accesstransistors 18 may be referred to as planar transistors due to thehorizontally-extending channel regions 26. In some embodiments, theaccess transistor 18 a may be considered to have first and secondsource/drain regions 22 a and 22 b which are spaced from one another bya horizontally-extending channel region 26 a; and the protectivetransistor 40 a may be considered to comprise third and fourthsource/drain regions 52 a and 54 a which are spaced from one another bya vertically-extending channel region 56 a.

The channel regions 56 correspond to the gated portions of the pillars42 (i.e., to gated portions of the lengths of semiconductor material44). In some embodiments, the channel regions 56 may be referred to asgated portions of the interconnects 28.

In some embodiments, the protective transistors 40 may be considered tobe examples of switches which control current flow along theinterconnects 28. Such switches may have a “closed” operational stateand an “open” operational state. The closed operational state willenable current flow between the capacitors 16 and the source/drainregions 22. In the shown embodiment, the “closing” of such switchescorresponds to providing appropriate voltages to the gates 49 to enablecurrent flow across the channel regions 56 between the source/drainregions 52 and 54. The memory cells 12 may be subjected to read/writeoperations, refresh operations, etc., while the switches are closed. Theopen operational state of the switches will preclude current flowbetween the capacitors 16 and the source/drain regions 22, and may beutilized to prevent undesired leakage (and associated data loss) fromthe capacitors 16 of memory cells 12 while the memory cells are in aresting mode (i.e., are in a non-accessed mode). In the shownembodiment, the “opening” of the switches corresponds to havinginsufficient voltage along the gates 49 to enable coupling of thesource/drain regions 52 and 54 across the channel regions 56.

In some embodiments, the protective transistors 40 may be utilized toalleviate, or even prevent, data loss from memory cells adjacent“hammered” rows; such as, for example, to avoid data loss from thememory cell 12 b along the wordline WL1 in applications in which theadjacent wordline WL0 is a “hammered” wordline.

In the shown embodiment, each of the protective transistors 40 has agate 49 which is electrically coupled with a gate 20 of an accesstransistor 18 within the same memory cell 12 as the protectivetransistor 40. For instance, the gate 20 a of the access transistorwithin the memory cell 12 a may be referred to as a first gate, and inthe embodiment of FIG. 6 is electrically coupled with a second gatecorresponding to the gate 49 a of the protective transistor 40 a withinthe memory cell 12 a.

In some embodiments, the first and second access transistors 18 a and 18b may be considered to comprise first and second gates 20 a and 20 b,respectively; and the protective transistors 40 a and 40 b may beconsidered to comprise third and fourth gates 49 a and 49 b,respectively. In the embodiment of FIG. 6 , the third gate 49 a iselectrically coupled with the first gate 20 a, and the fourth gate 49 bis electrically coupled with the second gate 20 b.

The various components of FIG. 6 may have any suitable architecturalrelationships relative to one another. For instance, the embodiment ofFIG. 6 shows the third and fourth gates 49 a and 49 b over the first andsecond gates 20 a and 20 b; and shows the digit line DL0 between theelevation of the third and fourth gates, and the elevation of the firstand second gates. In other embodiments, the digit line may be placed inany other suitable location. Also, the various gates 20 a, 20 b, 49 a,49 b, etc., may be placed in any suitable orientation relative to oneanother.

FIG. 7 schematically illustrates the memory array 10 of FIG. 6 . Theschematic illustration of FIG. 7 shows the protective transistor 40 ahaving a gate 49 a coupled with the same wordline (WL0) as the gate 20 aof the access transistor 18 a; and shows the protective transistor 40 bhaving a gate 49 b coupled with the same wordline (WL1) as the gate 20 bof the access transistor 18 b.

The capacitors 16 of FIG. 6 may have any suitable configuration. FIG. 8shows a region of the memory array 10 analogous to that of FIG. 6 , butillustrating a specific example configuration of the capacitors 16. Eachof the capacitors 16 comprises a first conductive node 58, a secondconductive node 60, and an insulative material 62 between the first andsecond conductive nodes. The first and second conductive nodes 60 and 62may comprise any suitable electrically conductive composition(s); suchas, for example, one or more of various metals (e.g., titanium,tungsten, cobalt, nickel, platinum, ruthenium, etc.), metal-containingcompositions (e.g., metal silicide, metal nitride, metal carbide, etc.),and/or conductively-doped semiconductor materials (e.g.,conductively-doped silicon, conductively-doped germanium, etc.). Thefirst and second conductive nodes may comprise the same composition asone another, or may comprise different compositions relative to oneanother. The insulative material 62 may comprise any suitablecomposition(s), and in some embodiments may comprise, consistessentially of, or consist of silicon dioxide.

In the shown embodiment, the lower conductive nodes 58 are configured asupwardly-opening containers. In other embodiments, the lower conductivenodes may have other suitable shapes. The lower conductive nodes 58 maybe referred to as storage nodes, and the upper nodes 60 may be referredto as plate electrodes. In some embodiments, the plate electrodes withinmemory array 10 may all be coupled to one another, and may be coupled toa reference voltage (e.g., the common plate voltage).

In some embodiments, the gates 49 of the protective transistors 40 maynot be coupled with the gates 20 of the access transistors 18, but mayinstead be coupled with multiplexer (mux) circuitry so that theprotective transistors may be separately controlled relative to theaccess transistors. For instance, FIG. 9 shows a region of the memoryarray 10 analogous to that of FIG. 6 , but in which the gates of theprotective transistors 40 are coupled with mux lines (mux0, mux1, mux2and mux3) which extend to a mux driver.

FIG. 10 shows a schematic illustration of the memory array 10 of FIG. 9, and shows that the mux wiring is coupled with the mux driver, whilethe wordlines are coupled with the row driver. The utilization of a muxdriver to control the protective transistors 40 may enable improvedoperational control of the protective transistors for sonicapplications. However, the utilization of the mux driver may increasethe complexity of fabrication as compared to architectures lacking themux driver (e.g., the architecture of FIG. 7 ). Accordingly, thearchitecture of FIG. 7 may be preferred in some applications, and thearchitecture of FIG. 10 may be preferred in other applications.

The capacitors 16 of FIG. 9 may have any suitable configuration. FIG. 11shows a region of the memory array 10 analogous to that of FIG. 9 , butillustrating a specific example configuration of the capacitors 16. Inthe shown embodiment of FIG. 11 , the capacitors 16 have an identicalconfiguration as that described above with reference to FIG. 8 .

The assemblies and structures discussed above may be utilized withinintegrated circuits with the term “integrated circuit” meaning anelectronic circuit supported by a semiconductor substrate); and may beincorporated into electronic systems. Such electronic systems may beused in, for example, memory modules, device drivers, power modules,communication modems, processor modules, and application-specificmodules, and may include multilayer, multichip modules. The electronicsystems may be any of a broad range of systems, such as, for example,cameras, wireless devices, displays, chip sets, set top boxes, games,lighting, vehicles, clocks, televisions, cell phones, personalcomputers, automobiles, industrial control systems, aircraft, etc.

Unless specified otherwise, the various materials, substances,compositions, etc. described herein may be formed with any suitablemethodologies, either now known or yet to be developed, including, forexample, atomic layer deposition (ALD), chemical vapor deposition (CVD),physical vapor deposition (PVD), etc.

The terms “dielectric” and “insulative” may be utilized to describematerials having insulative electrical properties. The terms areconsidered synonymous in this disclosure. The utilization of the term“dielectric” in some instances, and the term “insulative” (or“electrically insulative”) in other instances, may be to providelanguage variation within this disclosure to simplify antecedent basiswithin the claims that follow, and is not utilized to indicate anysignificant chemical or electrical differences.

The particular orientation of the various embodiments in the drawings isfor illustrative purposes only, and the embodiments may be rotatedrelative to the shown orientations in some applications. Thedescriptions provided herein, and the claims that follow, pertain to anystructures that have the described relationships between variousfeatures, regardless of whether the structures are in the particularorientation of the drawings, or are rotated relative to suchorientation.

The cross-sectional views of the accompanying illustrations only showfeatures within the planes of the cross-sections, and do not showmaterials behind the planes of the cross-sections, unless indicatedotherwise, in order to simplify the drawings.

When a structure is referred to above as being “on”, “adjacent” or“against” another structure, it can be directly on the other structureor intervening structures may also be present. In contrast, when astructure is referred to as being “directly on”, “directly adjacent” or“directly against” another structure, there are no interveningstructures present.

Structures (e.g., layers, materials, etc.) may be referred to as“extending vertically” to indicate that the structures generally extendupwardly from an underlying base (e.g., substrate). Thevertically-extending structures may extend substantially orthogonallyrelative to an upper surface of the base, or not.

Some embodiments include an integrated assembly having an accesstransistor. The access transistor has a first source/drain regiongatedly coupled with a second source/drain region. A digit line iscoupled with the first source/drain region. A charge-storage device iscoupled with the second source/drain region through an interconnect. Theinterconnect includes a length of a semiconductor material. A protectivetransistor gates a portion of the length of the semiconductor material.

Some embodiments include an integrated assembly which comprises a firstaccess transistor and a second access transistor. The first accesstransistor comprises a first gate proximate a first channel region, andthe second access transistor comprises a second gate proximate a secondchannel region. The first and second access transistors togethercomprise three source/drain regions, with one of the three source/drainregions being shared by the first and second access transistors. Thethree source/drain regions are a first source/drain region, a secondsource/drain region and a third source/drain region. The first andsecond source/drain regions are gatedly coupled to one another throughthe first channel region. The second and third source/drain regions aregatedly coupled to one another through the second channel region. Adigit line is coupled with the second source/drain region. A firstcharge-storage device is coupled with the first source/drain regionthrough a first interconnect. A second charge-storage device is coupledwith the third source/drain region through a second interconnect. Afirst switch controls current flow along the first interconnect. Asecond switch controls current flow along the second interconnect.

Some embodiments include an integrated assembly which comprises a firstaccess transistor and a second access transistor. The first accesstransistor comprises a first gate proximate a first channel region, andthe second access transistor comprises a second gate proximate a secondchannel region. The first and second access transistors togethercomprises three source/drain regions, with one of the three source/drainregions being shared by the first and second access transistors. Thethree source/drain regions are a first source/drain region, a secondsource/drain region and a third source/drain region. The first andsecond source/drain regions are gatedly coupled to one another throughthe first channel region. The second and third source/drain regions aregatedly coupled to one another through the second channel region. Thefirst channel region extends horizontally between the first and secondsource/drain regions. The second channel region extends horizontallybetween the second and third source/drain regions. A digit line iscoupled with the second source/drain region. A first capacitor iscoupled with the first source/drain region through a first interconnect.The first interconnect comprises a first vertically-extending pillar ofa first semiconductor material. A second capacitor is coupled with thethird source/drain region through a second interconnect. The secondinterconnect comprises a second vertically-extending pillar of a secondsemiconductor material. A first protective transistor gates a portion ofthe first vertically-extending pillar of the first semiconductormaterial. A second protective transistor gates a portion of the secondvertically-extending pillar of the second semiconductor material.

In compliance with the statute, the subject matter disclosed herein hasbeen described in language more or less specific as to structural andmethodical features. It is to be understood, however, that the claimsare not limited to the specific features shown and described, since themeans herein disclosed comprise example embodiments. The claims are thusto be afforded full scope as literally worded, and to be appropriatelyinterpreted in accordance with the doctrine of equivalents.

1-18. (canceled)
 19. An integrated assembly, comprising: a first transistor comprising a first gate and a source/drain region; an interconnect extending from the source/drain region to a charge-storage device; and a second transistor comprising a second gate that gates a portion of a length of the interconnect, the second gate electrically coupled to the first gate.
 20. The integrated assembly of claim 19 wherein the charge-storage device comprises a capacitor.
 21. The integrated assembly of claim 20 wherein the capacitor comprises an upper node that is not configured as an upwardly-opening container.
 22. The integrated assembly of claim 20 wherein the capacitor comprises an insulative material configured an upwardly-opening container and an upper node filling an entirety of the upwardly-opening container.
 23. The integrated assembly of claim 19 wherein the interconnect does not extend vertically.
 24. The integrated assembly of claim 19 wherein the interconnect comprises a first material over a second material, the second material being different form the first material.
 25. An integrated assembly, comprising: a first transistor comprising a source/drain region; an interconnect extending from the source/drain region and comprising at least: one or more of metals; a metal-containing material; or conductively-doped germanium; and a second transistor comprising a gate that gates a portion of the length of the interconnect.
 26. The integrated assembly of claim 25 wherein the first transistor comprises a first gate and the gate of the second transistor comprises a second gate, the first gate is electrically coupled to the second gate.
 27. The integrated assembly of claim 25 wherein the one or more of metals comprises titanium, tungsten, cobalt, nickel, platinum or ruthenium.
 28. The integrated assembly of claim 25 wherein the metal-containing material comprises metal silicide, metal nitride or metal carbide.
 29. The integrated assembly of claim 25 wherein the interconnect comprises conductively-doped germanium and at least: one or more of metals; or a metal-containing material.
 30. An integrated assembly, comprising: a first transistor comprising a first gate and a source/drain region; an interconnect comprising a first material and a second material different from the first material, the first material extending from the source/drain region; and a second transistor comprising a second gate that gates a portion of the interconnect at the second material.
 31. The integrated assembly of claim 30 wherein the first gate is electrically coupled to the second gate.
 32. The integrated assembly of claim 30 wherein the second material of the interconnect comprises conductively-doped germanium.
 33. The integrated assembly of claim 30 wherein the first material of the interconnect comprises at least: one or more of metals; or a metal-containing material.
 34. The integrated assembly of claim 30 wherein the second material of the interconnect comprises semiconductor material and the first material comprises at least: one or more of metals; or a metal-containing material. 